AREA OF SKILLS & KNOWLEDGE                         (Scroll down here)

LAN & WAN : T1/FT1/T3/OC3, ATM, TCP/IP, VoATM, VoDSL, GR303, SMDS,
Frame-Relay, HDSL2, xDSL, ISDN, PPP, MLPPP, Telephone, SS7.
Software : Real-time multi-task programming, high performance device
driver, RTOS (pSOS, VxWorks, US software, AMX).
Hardware : MPC8x60 PowerQUICC, M68360 QUICC, M68302, M68000,
8018X, IDT 30XX RISC, 80XX, TMS320CXX
Tools : Logical Analyzer, ICE, protocol analyzer, W&D-DA30, Ameritech call
generator

EXPERIENCE
Senior Member of Technical Staff
Caliper Technologies Corp., Mountain View, CA (2/03-present)
-Porting VxWorks real-time OS kernal to HTS260 platform.
-Design and implement real-time robotic motion control system in C/C++.

Software Director, embedded system group
ANDA Networks Inc., San Jose, CA (7/98-12/2002)
-Lead a team of engineers, in charge of firmware/software development for
all interface and server modules. Projects include: T1, E1, T3, DS3/ATM,
OC3/ATM, STM1/ATM, OC3/TDM, STM1/TDM, CDS server, AAL1 server, AAL2
server as well as V5.2 server.

-Responsible for setting up the R&D center in China, recruiting and built up a
peripheral group over there. Plan and coordinate technical transfer. Manage
projects on both sides.

-Initiated EtherEdge4000 project per Worldcom’s RFI. It is a Building Ethernet
Access System (BEAS) for Worldcom. It is an edge VLAN tag switch that
supports QoS and multiple-queue per VLAN base. Participated in RFI
response, system architecture and design. Lead the team in China to
implement all interface modules and low-level driver function modules for
EtherEdge4000 product. Modules include: driver for BCM5616, driver for
VT6510 switch chip, driver for QSPANII PCI bridge, 10/100 Base-T interface
(RTL8202), 100FX interface(RTL8202), GigE trunk, DS3(x.86) truck, OC3 trunk
and VDSL interface(PEF22824&22825).

-Implemented Loop-unbundling solution per Bell-South’s RFP
It provides ILEC an economical solution to drop off, grooming DS0s from its
TR08 lines without break TR08 line protection function. Participated in RFP
response, system architecture and design.

-Designed and implemented OCD (Optical Concentration Device) solution per
SBC’s RFI
It is a ATM concentrating device that concentrates multiple DSLAM trunks
into a single ATM DS3/OC3 trunk. It supports UNI3.1 VPC, VCC, VPI/VCI
translation, QoS as well as traffic policing. Participated in RPI response,
system architecture and design.

-HDSL2 module (partner with ADTRAN)
-Responsible for ANDA portion firmware development. The module supports
16 HDSL2 ports. It provides D4/ESF signaling translation, call processing,
call monitoring, and call aggregation. It also supports both voice and data
cross-connection. Designed and implemented driver for TDM cross-
connector, signaling monitoring task, translation task, clock source
management task, as well as call process task. Also designed dual port ram
communication drive between ANDA CPU and ADTRAN main controller.

-ATM server module
-Responsible for firmware design, implementation and system integration
testing for ATM server card. This module serves as a bridge between TDM
bus and cell bus. It enables the same low cost T1 & HDSL2 peripheral cards
to support multiple services (TDM & ATM). It supports 128 links between two
buses, and total up to 8,000 PVCs. It provides traffic policing and multi-class
of queuing (four queues per link).

-ATM DS3 & OC3 interface modules
-Responsible for software and firmware design, implementation as well as
system integration testing for ATM DS3 & OC3 modules. It has two DS3 or
OC3C ports with UNI 3.x interface. It supports traffic policing, traffic
scheduling, ILMI as well as F5/F4 OAM. It supports up to 8,000 PVCs.
Developed device driver for PMC QJET and cell bus interface FPGA.

-Voice over AAL1 & AAL2 gateway trunk & server modules
- Architecture and designed ANDA VoDSL solution. Responsible for software
design, implementation and system integration testing. This module supports
up to 24 T1 of AAL1 CES (circuit emulation service) or 576 channels of AAL2
LES (loop emulation service per ATM forum BLES standard). With daughter
card option, it can support ADPCM-32 over 576 voice channels.
Implemented TDM bus interface, call processing, call monitoring, as well as
call signaling processing. Developed device driver for PMCAAL1 SAR
device and cell header process FPGA.

-FTTH (Fiber To The Home) module for Optical Solution Inc (OSI).
This module is based on ANDA DS3 module. It replaces DS3 interface with
OSI’s PON fiber interface. Responsible for firmware develop and system
integration testing with OSI software team. Ported GR303 call processing
module, signaling monitoring module and call state machine. Designed dual
port ram communication interface between ANDA CPU and OSI CPU.

-DS3 module
It supports both voice and data channel grooming. It provides D4/ESF
signaling translation, call monitoring, and call aggregation. Played leading
role in firmware/software design, implementation and integration testing.
Developed device driver for M13 framer, TDM cross-connector. Implemented
call state-machine, signaling monitoring task, clock source management
task.

-T1 module
It supports both voice and data channels, provides D4/ESF signaling
translation, call processing, call monitoring, and call aggregation. Played
leading role in firmware/software architecture, design, implementation and
system integration testing. Designed call state-machine that inter-works with
GR303 engine on system module. Designed device driver for T1 framer
driver and TDM cross-connector. Implemented signaling monitoring task,
alarm monitoring, performance monitoring, timing source management task.
Also implemented driver for echo cancellation daughter card in order to
support VoATM application.

-Implemented MPC860 TSA (timer slot assignor) driver for system module, it
interfaces to TMC and EOC management channels on TDM bus.

-Worked closely with HW engineers to bring-up and debug hardware for
various TDM, ATM and server modules. Designed and implemented FPGA
initial and download module. Provides various debug interface for HW
engineers testing FPGA and other function modules.

-Responsible for porting pSOS BSP, establishing system platform and
development environment (using pSOS pRISM+ and Sniff, MPC860
PowerQUICC). The platform includes boot-up code, diagnostics, a serial
console port, a 10Base-T Ethernet port, as well as a HDLC communication
port.

Senior Firmware Engineer & Group Leader & Manager
Verilink Corporation, San Jose, CA (2/95-7/98)
-Initiated voice compression server project
(using MPC860 PowerQUICC, pSOS pRISM+ and 3rd party voice
compression processor)

-In charge of software design, implementation and integration for HDSL/T1
project.
(using 68360, PMC framer PM4344, and PairGain OEM module)

-Software architecture for ISDN bonding project on PEP (Protocol Engine
Processor) module. Developed DMA driver for bonding information channel
handler, and delay equalizer.

-Initiated Protocol Engine Processor (PEP) project. Worked with HW
engineers to bring-up and diagnostic Protocol Engine Processor (PEP)
module.

-In charge of firmware developing for M13 multiplex module. Worked with
HW engineers to debug and diagnostic the board. Designed and implemented
real-time on board FPGA download method.

-Responsible for firmware development and system integration of DS3
DSU/CSU module (using pSOS on M68360 QUICC); including SNMP, CRAFT
interface, DS3 line performance monitoring, PMC framer driver, QUICC HDLC
driver, DS3 data-link, and inband communication.

-In charge of system integrating for DS3/ATM PHY module (using M68360
QUICC w/pSOS) & SAR (Segmentation and Reassemble) module (using
IDT3071 & Fujitsu MB86687); including PMC framer driver, QUICC HDLC
driver, SNMP, MIBs, ILMI, LMI, F4 & F5 OAM, traffic shaping, DS3
performance monitoring, CRAFT interface.

-Designed and implemented IWF software for DS3/ATM SAR module on IDT
3071 RISC microprocessor; including DXI FIFO device driver, DXI HDLC
driver, packet DMA driver, ILMI & LMI processing.

-Developed ATM Adaptation Layer driver for Fujitsu ALC chip (MB86687) on
IDT 3071 RISC. It supports AAL5, 1023 VCs, F4 & F5 OAM, traffic shaping.

-Worked closely with HW engineer, developed a simulation model to
evaluate various memory interface to be used with Fujitsu ALC chip. This
effort resulted in the proposal of a fast SRAM memory interface, which has
since been implemented and proven out.

-Responsible for system integrating of DS3/SMDS PHY module (using
M68360 w/pSOS) & SAR (Segmentation and Reassemble) module; including
DS3 line performance monitoring, SNMP agent & MIBS, CRAFT interface,
inter-processor communication.

-Developed high performance SMDS SNI device driver and IWF (Inter-
Working Function) software for DS3/SMDS SAR module on IDT 3041/3071
RISC microprocessor; including DXI FIFO device driver, DXI HDLC driver,
packet DMA driver, the SMDS DXI PDU processing, keep-alive protocol and
flow control protocol. Also designed and implemented the SAR board
Download task which includes the flash memory driver, system boot
sequence, and file transfer.

-Worked with HW engineers to bring-up and debug the hardware for the
DS3/SMDS SAR module.

Software Project Engineer & Software Engineer
T-COM Corporation. Mountain View, CA (7/92-2/95)
-Designed & implemented real-time software for a multi-processor T1 test
equipment in C & assembly with Motorola 68000 & Intel 80188.
-Designed & implemented real-time control software for DS0 VF channel
monitor board.
-Ported & updated TMS320C25 code to support the new HW for DS0 VF
channel monitor board.
-Designed & implemented code down-loading feature for multi-processor T1
& T3 test equipment.
-Designed & implemented remote control feature on T1 & T3 test equipment.
-Designed & implemented PC resident real-time remote control software
(C++, MS/Window) for T1 & T3 test equipment.
-Developed a numerous programs for H/W testing and manufacturing testing.

Software Engineer
BAEKON, INC., Fremont, CA (5/91-6/92)
-Designed & implemented the real-time operating control software for biotech
research instrument, in C, assembly with 80188.
-Designed & implemented demonstration and tutorial package in C++ on PC.